Field
The present application relates to techniques and devices for performing arithmetic. Some embodiments disclosed in the application relate particularly to techniques and devices for performing arithmetic using programmable logic devices.
Related Art
Computing devices are sometimes used to perform computationally-intensive tasks, including, without limitation, digital signal processing (DSP), video processing, and/or image processing. In many tasks, including many computationally-intensive tasks, a significant portion of a computing device's processing resources are used to perform addition and/or multiplication operations.
Programmable logic devices are logic devices which can be programmed to perform different operations. The field programmable gate array (FPGA) is one example of a programmable logic device. FPGAs may be used to perform digital signal processing, video processing, image processing, encryption/decryption, floating-point operations and/or other tasks, including other computationally intensive tasks. Specific examples of such tasks include radar, high-definition television, facial recognition, and others. These tasks may use Finite-Impulse Response (FIR) and Infinite-Impulse Response (IIR) filters, the Fast Fourier Transform (FFT), the Discrete Cosine Transform (DCT), wavelet transforms, etc., which may include a large number of multiply and/or accumulate operations. Multiply operations may be performed using multiplier devices. Accumulation operations may be performed using adder devices. Some FPGAs include embedded adders and/or multipliers that are not programmable. Some FPGAs can be programmed to implement one or more adders and/or multipliers using the FPGA's lookup tables (LUTs). In some circumstances, the flexibility of LUT-based adders and/or multipliers may be advantageous.
U.S. Pat. Nos. 5,754,459 and 8,352,532 describe multipliers for FPGAs.